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(R)
LY61L5128
Rev. 2.2
512K X 8 BIT HIGH SPEED CMOS SRAM
REVISION HISTORY
Revision Rev. 1.0 Rev. 1.1 Rev. 2.0 Description Initial Issue Revised Package Outline Dimension(TSOP-II) Revised ICC and ISB1 Revised Test Condition of ISB1/IDR Added E and I grade Revised ABSOLUTE MAXIMUN RATINGS Adding PKG type : 36-ball 6mm x 8mm TFBGA Revised Test Condition of ICC Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Added packing type in ORDERING INFORMATION Issue Date Sep.5.2006 Apr.12.2007 Jun.23.2007
Rev. 2.1 Rev. 2.2
Mar.31.2008 Apr.17.2009
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0
(R)
LY61L5128
Rev. 2.2
512K X 8 BIT HIGH SPEED CMOS SRAM
GENERAL DESCRIPTION
The LY61L5128 is a 4,194,304-bit low power CMOS static random access memory organized as 524,288 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY61L5128 is well designed for very low power system applications, and particularly well suited for battery back-up nonvolatile memory application. The LY61L5128 operates from a single power supply of 3.3V and all inputs and outputs are fully TTL compatible
FEATURES
Fast access time : 10/12/15/20/25ns Very low power consumption: Operating current(Normal version): 180/160/140/80/70mA(MAX.) Standby current: 12mA(MAX. for 10/12/15ns) 5mA(MAX. for 20/25ns) 100A( (MAX. for 20/25ns LL version) Single 3.3V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data retention voltage : 2.0V (MIN.) Green package available Package : 32-pin 8mm x 20mm TSOP-I 32-pin 8mm x 13.4mm STSOP 44-pin 400 mil TSOP-II 36-ball 6mm x 8mm TFBGA
PRODUCT FAMILY
Product Operating Family Temperature 0 ~ 70 LY61L5128 -20 ~ 80 LY61L5128(E) -40 ~ 85 LY61L5128(I) 0 ~ 70 LY61L5128 -20 ~ 80 LY61L5128(E) -40 ~ 85 LY61L5128(I) 0 ~ 70 LY61L5128(LL) LY61L5128(LLE) -20 ~ 80 LY61L5128(LLI) -40 ~ 85 Vcc Range 3.15/3.0 ~ 3.6V 3.15/3.0 ~ 3.6V 3.15/3.0 ~ 3.6V 3.0 ~ 3.6V 3.0 ~ 3.6V 3.0 ~ 3.6V 3.0 ~ 3.6V 3.0 ~ 3.6V 3.0 ~ 3.6V Speed 10/12/15ns 10/12/15ns 10/12/15ns 20/25ns 20/25ns 20/25ns 20/25ns 20/25ns 20/25ns Power Dissipation Standby(ISB1,MAX.) Operating(Icc,MAX.) 12mA 180/160/140mA 12mA 180/160/140mA 12mA 180/160/140mA 5mA 80/70mA 5mA 80/70mA 5mA 80/70mA 100A 80/70mA 100A 80/70mA 100A 80/70mA
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1
(R)
LY61L5128
Rev. 2.2
512K X 8 BIT HIGH SPEED CMOS SRAM
PIN DESCRIPTION
SYMBOL DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Inputs Write Enable Input Output Enable Input Power Supply Ground No Connection
FUNCTIONAL BLOCK DIAGRAM
Vcc Vss
A0 - A18 DQ0 - DQ7
DECODER 512Kx8 MEMORY ARRAY
CE# WE# OE# VCC VSS NC
A0-A18
DQ0-DQ7
I/O DATA CIRCUIT
COLUMN I/O
CE# WE# OE#
CONTROL CIRCUIT
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2
(R)
LY61L5128
Rev. 2.2
512K X 8 BIT HIGH SPEED CMOS SRAM
PIN CONFIGURATION
NC NC A4 A3 A2 A1 A0 CE# DQ0 DQ1 Vcc Vss DQ2 DQ3 WE# A18 A17 A16 A15 A14 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 TSOP-II 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A5 A6 A7 A8 OE# DQ7 DQ6 Vss Vcc DQ5 DQ4 A9 A10 A11 A12 A13 NC NC NC
LY61L5128
A B C D E F G H
A0 DQ4 DQ5 Vss Vcc DQ6
A1 A2
NC WE# NC
A3 A4 A5
A6 A7
A8 DQ0 DQ1 Vcc Vss
A18
A17
DQ2 A15 DQ3 A13 A14
DQ7 OE# CE# A16 A9 A10 A11 A12
1
2
3 4 TFBGA
5
6
A11 A9 A8 A13 WE# A17 A15 Vcc A18 A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
LY61L5128
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A3
TSOP-I/STSOP
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3
(R)
LY61L5128
Rev. 2.2
512K X 8 BIT HIGH SPEED CMOS SRAM
ABSOLUTE MAXIMUN RATINGS*
PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 TA TSTG PD IOUT RATING -0.5 to 4.6 -0.5 to VCC+0.5 0 to 70(C grade) -20 to 80(E grade) -40 to 85(I grade) -65 to 150 1 50 UNIT V V W mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE Standby Output Disable Read Write
Note:
CE# H L L L
OE# X H L X
WE# X H H L
I/O OPERATION High-Z High-Z DOUT DIN
SUPPLY CURRENT ISB1 ICC ICC ICC
H = VIH, L = VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
PARAMETER Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Average Operating Power supply Current SYMBOL VCC VIH *2 VIL ILI ILO VOH VOL
*1
TEST CONDITION 10/12 15/20/25
VCC VIN VSS VCC VOUT VSS, Output Disabled IOH = -4mA IOL = 8mA Cycle time = Min. CE# = VIL , II/O = 0mA others at VIH or VIL 10 12 15 20 25 10/12/15 CE# VCC - 0.2V, 20/25 others at 0.2V or VCC - 0.2V 20/25LL
MIN. 3.15 3.0 2.2 - 0.3 -1 -1 2.4 -
TYP. 3.3 3.3 50 45 0.5 20
*4
MAX. 3.6 3.6 VCC+0.3 0.6 1 1 0.4 180 160 140 80 70 12 5 5* 6 100*
UNIT V V V V A A V V mA mA mA mA mA mA mA A
ICC
Standby Power Supply Current
ISB1
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4
(R)
LY61L5128
Rev. 2.2
512K X 8 BIT HIGH SPEED CMOS SRAM
Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25 5. 1mA for special request 6. 50A for special request
CAPACITANCE (TA = 25, f = 1.0MHz)
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN.
-
MAX 8 10
UNIT pF pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -8mA/16mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE PARAMETER
Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LY61L5128 -10 LY61L5128 -12 LY61L5128 -15 LY61L5128 -20 LY61L5128 UNIT -25
SYM.
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. tRC 10 12 15 20 25 ns tAA 10 12 15 20 25 ns tACE 10 12 15 20 25 ns tOE 5 6 7 8 9 ns tCLZ* 2 3 4 4 4 ns tOLZ* 0 0 0 0 0 ns tCHZ* 5 6 7 8 9 ns tOHZ* 5 6 7 8 9 ns tOH 3 3 3 3 3 ns
(2) WRITE CYCLE PARAMETER
Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z
SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ*
LY61L5128 -10
LY61L5128 -12
LY61L5128 -15
LY61L5128 -20
LY61L5128 UNIT -25
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. 10 12 15 20 25 8 10 12 16 20 8 10 12 16 20 0 0 0 0 0 8 9 10 11 12 0 0 0 0 0 6 7 8 9 10 0 0 0 0 0 2 3 4 5 6 6 7 8 9 10
ns ns ns ns ns ns ns ns ns ns
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5
(R)
LY61L5128
Rev. 2.2
512K X 8 BIT HIGH SPEED CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC Address tAA Dout Previous Data Valid tOH Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
tRC Address tAA CE# tACE OE# tOE tOLZ tCLZ Dout High-Z tOH tOHZ tCHZ Data Valid High-Z
Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low. 3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured 500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6
(R)
LY61L5128
Rev. 2.2 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC Address tAW CE# tCW tAS WE# tWHZ Dout (4) High-Z tDW Din tDH TOW (4) tWP tWR
512K X 8 BIT HIGH SPEED CMOS SRAM
Data Valid
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)
tWC Address tAW CE# tAS tCW tWP WE# tWHZ Dout (4) High-Z tDW Din tDH tWR
Data Valid
Notes : 1.WE#, CE# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7
(R)
LY61L5128
Rev. 2.2
512K X 8 BIT HIGH SPEED CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER SYMBOL TEST CONDITION VCC for Data Retention VDR CE# VCC - 0.2V 10/12/15 VCC = 2.0V CE# VCC - 0.2V Data Retention Current IDR 20/25 others at 0.2V or VCC - 0.2V 20/25LL See Data Retention Chip Disable to Data tCDR Waveforms (below) Retention Time Recovery Time tR tRC* = Read Cycle Time MIN. 2.0 0 tRC* TYP. 0.5 10 MAX. 3.6 1 50 UNIT V mA mA A ns ns
DATA RETENTION WAVEFORM
VDR 2.0V Vcc Vcc(min.) tCDR CE# VIH CE# Vcc-0.2V Vcc(min.) tR VIH
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8
(R)
LY61L5128
Rev. 2.2
512K X 8 BIT HIGH SPEED CMOS SRAM
PACKAGE OUTLINE DIMENSION
32 pin 8mm x 20mm TSOP-I Package Outline Dimension
UNIT SYM.
INCH(BASE) 0.047 (MAX) 0.004 0.002 0.039 0.002 0.008 + 0.002 - 0.001 0.005 (TYP) 0.724 0.004 0.315 0.004 0.020 (TYP) 0.787 0.008 0.0197 0.004 0.0315 0.004 0.003 (MAX) o o 0 5
MM(REF) 1.20 (MAX) 0.10 0.05 1.00 0.05 0.20 + 0.05 -0.03 0.127 (TYP) 18.40 0.10 8.00 0.10 0.50 (TYP) 20.00 0.20 0.50 0.10 0.08 0.10 0.076 (MAX) o o 0 5
A A1 A2 b c D E e HD L L1 y
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9
(R)
LY61L5128
Rev. 2.2
512K X 8 BIT HIGH SPEED CMOS SRAM
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
HD
c L
12 (2x)
1 32
12 (2x)
e
16 17
"A"
D Seating Plane
b
E
y
12 (2X)
16
17
GAUGE PLANE A A2 c 0.254 0 A1 SEATING PLANE 12 (2X) L1 L
"A" DATAIL VIEW
1 32
UNIT SYM.
INCH(BASE) 0.049 (MAX) 0.005 0.002 0.039 0.002 0.008 0.01 0.005 (TYP) 0.465 0.004 0.315 0.004 0.020 (TYP) 0.5280.008 0.0197 0.004 0.0315 0.004 0.003 (MAX) o o 0 5
MM(REF) 1.25 (MAX) 0.130 0.05 1.00 0.05 0.200.025 0.127 (TYP) 11.80 0.10 8.00 0.10 0.50 (TYP) 13.40 0.20. 0.50 0.10 0.8 0.10 0.076 (MAX) o o 0 5
A A1 A2 b c D E e HD L L1 y
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10
(R)
LY61L5128
Rev. 2.2
512K X 8 BIT HIGH SPEED CMOS SRAM
44-pin 400mil TSOP- Package Outline Dimension
SYMBOLS A A1 A2 b c D E E1 e L ZD y
DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 o o o 3 6 0
DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.3 11.8 17.7 4.7 8.3 717 725 733 453 463 473 392 400 408 31.5 15.7 19.7 23.6 31.7 3 o o o 0 3 6
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 11
(R)
LY61L5128
Rev. 2.2
512K X 8 BIT HIGH SPEED CMOS SRAM
36 ball 6mm x 8mm TFBGA Package Outline Dimension
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 12
(R)
LY61L5128
Rev. 2.2
512K X 8 BIT HIGH SPEED CMOS SRAM
ORDERING INFORMATION
LY61L5128 U V - WW XX Y Z
Z : Packing Type Blank : Tube or Tray T : Tape Reel Y : Temperature Range Blank : (Commercial) 0C ~ 70C E : (Extended) -20C ~ +80C I : (Industrial) -40C ~ +85C XX : Power Type LL : Ultra Low Power WW : Access Time(Speed) V : Lead Information L : Green Package U : Package Type L : 32-pin 8 mm x 20 mm TSOP-I R : 32-pin 8 mm x 13.4 mm STSOP M : 44-pin 400 mil TSOP-II G : 36-ball 6 mm x 8 mm TFBGA
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 13
(R)
LY61L5128
Rev. 2.2
512K X 8 BIT HIGH SPEED CMOS SRAM
THIS PAGE IS LEFT BLANK INTENTIONALLY.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 14

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